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MC74VHCT138A 3-to-8 Line Decoder
The MC74VHCT138A is an advanced high speed CMOS 3-to-8 decoder fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. When the device is enabled, three Binary Select inputs (A0 - A2) determine which one of the outputs (Y0 - Y7) will go Low. When enable input E3 is held Low or either E2 or E1 is held High, decoding function is inhibited and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade connection and for use as an address decoder for memory systems. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because they have full 5.0 V CMOS level output swings. The VHCT138A input structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc.
Features
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16 SOIC-16 D SUFFIX CASE 751B 1 1 16 TSSOP-16 DT SUFFIX CASE 948F 1 1 VHCT 138A ALYWG G VHCT138AG AWLYWW
* * * * * * * * * * *
High Speed: tPD = 7.6 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 V to 5.5 V Operating Range Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 122 FETs or 30.5 Equivalent Gates Pb-Free Packages are Available*
A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
PIN ASSIGNMENT
A0 A1 A2 E1 E2 E3 Y7 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6
ORDERING INFORMATION
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
1
January, 2006 - Rev. 3
Publication Order Number: MC74VHCT138A/D
MC74VHCT138A
FUNCTION TABLE
Inputs E3 X X L H H H H H H H H E2 X H X L L L L L L L L H X X L L L L L L L L X X X L L L L H H H H X X X L L H H L L H H X X X L H L H L H L H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H Outputs H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L ENABLE INPUTS E3 E2 E1 6 5 4 SELECT INPUTS A0 A1 A2 1 2 3 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
LOGIC DIAGRAM
15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 7 Y7
ACTIVE-LOW OUTPUTS
H = high level (steady state); L = low level (steady state); X = don't care
EXPANDED LOGIC DIAGRAM
15
Y0
14
Y1
A0
1
13
Y2
A1
2
12
Y3
A2
3
11
Y4
10 E2 E1 5 4 9
Y5
Y6
7
Y7
E3
6
IEC LOGIC DIAGRAM
A0 A1 A2 1 2 3 BIN/OCT 1 2 4 & EN 0 1 2 3 E3 E2 E1 6 5 4 4 5 6 7 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 7 Y7 E3 E2 E1 6 5 4 A0 A1 A2 1 2 3 DMUX 0 2 & 0 G 7 0 1 2 3 4 5 6 7 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 7 Y7
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MC74VHCT138A
NORMALIZED FAILURE RATE
TJ = 130 C
TJ = 120 C
TJ = 110 C
90 100 110 120 130 140
419,300 178,700 79,600 37,000 17,800 8,900
47.9 20.4 9.4 4.2 2.0 1.0
1 1 10 TIME, YEARS 100 1000
Figure 1. Failure Rate vs. Time Junction Temperature
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TJ = 80 C
TJ = 90 C
80
1,032,200
117.8
TJ = 100 C
II I I IIIIIIIIIIIIIIIIIIIIIII II III I II I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I III IIIIIIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I III II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII IIIIIII I IIII IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
VCC Vin SymbolIIIIIIIIIIIIII Parameter DC Supply Voltage DC Input Voltage Value Unit V V V - 0.5 to + 7.0 - 0.5 to + 7.0 Vout IIK DC Output Voltage VCC = 0 High or Low State - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 20 20 25 75 500 450 Input Diode Current mA mA mA mA IOK Iout Output Diode Current (VOUT < GND; VOUT > VCC) DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package mW _C Tstg - 65 to + 150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating - SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
III I I I I IIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III IIIII IIIIIIIIIIIIIIIIIIIIIII I III I I II I I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII III I I IIIII I III IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I
Symbol VCC Vin Parameter Min 3.0 0 0 0 Max 5.5 5.5 Unit V V V DC Supply Voltage DC Input Voltage Vout TA DC Output Voltage VCC = 0 High or Low State 5.5 VCC Operating Temperature - 55 0 + 125 20 _C tr, tf Input Rise and Fall Time VCC =5.0V 0.5V ns/V
RECOMMENDED OPERATING CONDITIONS
The qJA of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and figure below.
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES
Junction Temperature C Time, Hours Time, Years FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR
II I II I II I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIII I II I I II IIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II III IIIIIIIIIII IIII II I I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I IIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIII I IIII IIIIII IIIIIIIIII II I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIII IIIIIIIIIII I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I IIII I IIIIIIIIIII I I II I I II I I IIII IIIIIIIII I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I I II I IIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII I II I I II I II I I II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIII I IIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII I I IIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I I II I II I I II I I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I I I II I II I I II I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I II I II I I II I I I II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I I I I I IIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I II I I I I I I IIIIIII I I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII II I I I IIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I II I I I II I I II I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) DC ELECTRICAL CHARACTERISTICS
Symbol Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL IOPD ICCT VOH CPD VOL CIN VIH ICC VIL IIN Power Dissipation Capacitance (Note 1) Maximum Input Capacitance Maximum Propagation Delay, Input E1 or E2 to Y Maximum Propagation Delay, Input E3 to Y Maximum Propagation Delay, Input A to Y Output Leakage Current Quiescent Supply Current Maximum Quiescent Supply Current Maximum Input Leakage Current Maximum Low-Level Output Voltage VIN = VIH or VIL Minimum High-Level Output Voltage VIN = VIH or VIL Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter Parameter VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VOUT = 5.5 V VIN = 3.4 V VIN = VCC or GND VIN = 5.5 V or GND VIN = VIH or VIL IOL = 4 mA IOL = 8 mA VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOH = -4 mA IOH = -8 mA VIN = VIH or VIL IOH = -50 mA Test Conditions Test Conditions
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
MC74VHCT138A
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CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF 0 to 5.5 VCC (V) 0.0 5.5 5.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 5.5 3.0 4.5 5.5 2.58 3.94 Min Min 2.9 4.4 1.4 2.0 2.0 TA = 25C TA = 25C 9.5 10.8 10.1 9.9 Typ Typ 7.0 7.5 6.6 7.1 9.7 9.5 7.6 8.1 0.0 0.0 3.0 4.5 4 Typical @ 25C, VCC = 5.0V 0.1 9.6 10.6 14.0 15.0 9.1 10.1 13.0 14.0 10.4 11.4 14.5 15.5 Max 1.35 0.36 0.36 Max 0.53 0.8 0.8 0.5 4.0 0.1 0.1 10 TA = 85C 2.48 3.80 Min Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.9 4.4 1.4 2.0 2.0 49 TA 85C 1.0 11.0 12.0 15.5 16.5 10.5 11.5 14.5 15.5 12.0 13.0 16.0 17.0 Max 1.50 40.0 0.44 0.44 Max 0.53 0.8 0.8 5.0 0.1 0.1 10 2.34 3.66 Min Min TA 125C TA 125C 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.9 4.4 1.4 2.0 2.0 1.0 11.0 12.0 15.5 16.5 10.5 11.5 14.5 15.5 12.0 13.0 16.0 17.0 Max 1.50 40.0 0.52 0.52 Max 0.53 0.8 0.8 5.0 0.1 0.1 10 Unit Unit mA mA mA mA pF pF ns ns ns V V V V V V
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MC74VHCT138A
SWITCHING WAVEFORMS
VALID A tPLH Y 1.5V 1.5V tPHL VOH VOL Y VALID 3V GND E3 tPHL 1.5V 1.5V tPLH 3V GND VOH VOL
Figure 2.
Figure 3.
E2 or E1
1.5V tPHL tPLH
3V GND VOH VOL
Y
1.5V
Figure 4.
TEST POINT OUTPUT DEVICE UNDER TEST C L*
*Includes all probe and jig capacitance
Figure 5. Test Circuit
ORDERING INFORMATION
Device MC74VHCT138ADR2 MC74VHCT138ADR2G MC74VHCT138ADTR2 MC74VHCT138ADTRG Package SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* TSSOP-16* Shipping 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74VHCT138A
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC74VHCT138A
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE A
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
16 9
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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CCC EEE CCC EEE CCC
K1
SECTION N-N
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC74VHCT138A/D

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